`timescale 1ns/100ps
`default_nettype none

module tb_Interpolation;

logic _Clock_50;
logic _resetn;

logic [31:0] _R[5:0];

logic _start;

logic [31:0] _mulResult;
logic [31:0] _mulOp1;
logic [31:0] _mulOp2;

logic [31:0] _intResult;
logic _finish;


Interpolation uut (
    .CLOCK_50_I(_Clock_50),
    .resetn(_resetn),
    .R(_R),
    
    .start(_start),
    
    .mulResult(_mulResult),
    .mulOp1(_mulOp1),
    .mulOp2(_mulOp2),

    .intResult(_intResult),
    .finish(_finish)
);

Mul32 mul32uut (
    .op1(_mulOp1),
    .op2(_mulOp2),
    .result(_mulResult)
);

// Generate a 50 MHz clock
always begin
	# 10;
	_Clock_50 = ~_Clock_50;
end

task master_reset;
begin
	wait (_Clock_50 !== 1'bx);
	@ (posedge _Clock_50);
	_resetn = 1'b0;
	// Activate reset for 2 clock cycles
	@ (posedge _Clock_50);
	@ (posedge _Clock_50);	
	_resetn = 1'b1;	
end
endtask

task start_interpolation;
begin
    wait (_Clock_50 !== 1'bx);
    @ (posedge _Clock_50);
    _start = 1'b1;
    // Activate start for 1 clock cycles
	@ (posedge _Clock_50);
    _start = 1'b0;
end
endtask

// Initialize signals
initial begin
    _Clock_50 = 1'b0;
    _R[0] = 32'd131;
    _R[1] = 32'd185;
    _R[2] = 32'd168;
    _R[3] = 32'd178;
    _R[4] = 32'd185;
    _R[5] = 32'd159;
    
    // Apply master reset
    $write("Applying master reset...\n");
    master_reset;
    // Apply start signal
    $write("Giving start signal...\n");
    start_interpolation;

    @ (posedge uut.finish);
    $write("Interpolation is done. Expect 143.\n");
    $stop;
end

endmodule
